Design of Least Complex S - Box and its Fault Detection for Robust AES Algorithm

Advanced Encryption Standard (AES) is the symmetric key standard for encryption and decryption. In this work, a 128-bit AES encryption and decryption using Rijndael Algorithm is designed and synthesized using verilog code. The fault detection scheme for their hardware implementation plays an important role in making the AES robust to the internal and malicious faults. In the proposed AES, a composite field S-Box and inverse S-Box is implemented using logic gates and divided them into five blocks. Any natural or malicious faults which defect the logic gates are detected using parity based fault detection scheme. For increasing the fault exposure, the predicted parities of each of the block S-box and inverse S-box are obtained. The multi-bit parity prediction approach has low cost and high error coverage than the approaches using single bit parities. The Field Programmable Gate Array (FPGA) implementation of the fault detection structure has better hardware and time complexities.